EP610ILC-10 vs EP610DC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610ILC-10 sa pamamagitan ng Altera at EP610DC-20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610ILC-10 | EP610DC-20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Classic EPLD | — |
| Product Type | UV-Erasable / OTP PLD | CMOS UV-Erasable Programmable Logic Device (EPLD) |
| Architecture | PAL-type with macrocells | — |
| Macrocells | 16 | — |
| Usable Gates | 300 | — |
| Product Terms | 160 | — |
| I/O Pins | 16 | 16 (bidirectional) |
| Dedicated Inputs | 4 | 4 |
| Volte ng Pagbibigay | 5 V (single supply) | — |
| Pin-to-Pin Delay (tPD) | 10 ns (grade -10) | — |
| Counter Frequency (fCNT) | 100 MHz | — |
| Logic Family Compatibility | TTL (5 V CMOS/TTL-compatible I/O) | — |
| Packhaging | PLCC-28 (plastic J-lead chip carrier) | 24-pin Ceramic DIP (CDIP-24) with UV window |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or solder) | Through-hole |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 °C to 70 °C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance status] |
| Family | — | Classic EP610 |
| Logic Macrocells | — | 16 |
| Total Usable Pins | — | 20 |
| Product Terms (p-terms) | — | 160 |
| Propagation Delay (tPD) | — | 22 ns |
| Maximum Toggle Frequency (fMAX) | — | 55.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Programming Method | — | UV erasure + parallel programmer |
| Process Technology | — | CMOS, UV-erasable floating gate |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |