EP610IPC-25 vs EP610ILC-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610IPC-25 sa pamamagitan ng Intel at EP610ILC-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP610IPC-25 | EP610ILC-10 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Classic EPLD (EP610) | — |
| Architecture | PAL-type, CMOS, Erasable | PAL-type with macrocells |
| Propagation Delay (tpd) | 25 ns (max) | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Maximum Inputs | 20 | — |
| Maximum I/O Pins | 16 | — |
| Dedicated Outputs | 16 | — |
| Product Terms | 160 | 160 |
| Temperature na Operasyon | 0 °C to +70 °C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Packhaging | 24-pin PDIP (Plastic DIP) | PLCC-28 (plastic J-lead chip carrier) |
| Technology | CMOS, UV-erasable (windowless in IPC pkg) | — |
| TTL Compatibility | 100% TTL emulation | — |
| Uri ng Pagpapasok | Through-Hole | Surface Mount (PLCC socket or solder) |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | Non-compliant (contains Pb, PDIP package) | [DATA_NEEDED: RoHS compliance] |
| Logic Capacity | Equivalent to ~24 standard 24-pin PALs | — |
| Device Family | — | Classic EPLD |
| Product Type | — | UV-Erasable / OTP PLD |
| Macrocells | — | 16 |
| Usable Gates | — | 300 |
| I/O Pins | — | 16 |
| Dedicated Inputs | — | 4 |
| Volte ng Pagbibigay | — | 5 V (single supply) |
| Pin-to-Pin Delay (tPD) | — | 10 ns (grade -10) |
| Counter Frequency (fCNT) | — | 100 MHz |
| Logic Family Compatibility | — | TTL (5 V CMOS/TTL-compatible I/O) |