EP610JI-30 vs EP610IPC-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610JI-30 sa pamamagitan ng Altera at EP610IPC-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610JI-30 EP610IPC-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family Altera Classic EPLD (EP610) Altera Classic EPLD
Device Type UV Erasable Programmable Logic Device (EPLD) EPLD (Erasable Programmable Logic Device)
Macrocells 16 16
Propagation Delay (tpd) 30 ns (max) —
Pipelined Data Rate Up to 100 MHz —
Product Terms 160 160 total
Dedicated Inputs 4 4
I/O Pins 16 16
External Clocks 2 —
Volte ng Pagbibigay 5 V (single supply) 5 V
Process Technology CMOS —
Packhaging CQCC28 (windowed ceramic JLCC, J-bend) 24-pin PDIP (Plastic DIP)
Package Code JLCC-28 / CQCC28 —
Erasure Method Ultraviolet (UV) via top window —
Programming Altera Logic Programmer compatible —
Temperature na Operasyon -40C to +85C (industrial, per EP610 family suffix convention) -40C to +85C (industrial)
Uri ng Pagpapasok Surface Mount (JLCC) —
Tindminan RoHS [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] —
Lead-Free [DATA_NEEDED: lead-free status] —
Programmable Gates — 300 usable gates
Maximum Operating Frequency — 100 MHz
Propagation Delay (tPD) — 15 ns (commerical -10 grade)
Total Input Pins — 20
Architecture — Turbo-only AND-OR-NOT, PAL-type
Technology — CMOS EPROM (UV-erasable / OTP)
Programming Method — Altera programming hardware (UV erase for I grade, OTP for C grade)
TTL Emulation — 100% TTL compatible

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