EP610JI-30 vs EP610LC-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610JI-30 sa pamamagitan ng Altera at EP610LC-30 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610JI-30 EP610LC-30
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family Altera Classic EPLD (EP610) Classic EPLD (EP610)
Device Type UV Erasable Programmable Logic Device (EPLD) —
Macrocells 16 —
Propagation Delay (tpd) 30 ns (max) —
Pipelined Data Rate Up to 100 MHz up to 100 MHz
Product Terms 160 —
Dedicated Inputs 4 —
I/O Pins 16 —
External Clocks 2 —
Volte ng Pagbibigay 5 V (single supply) —
Process Technology CMOS —
Packhaging CQCC28 (windowed ceramic JLCC, J-bend) 24-pin CERDIP / PDIP
Package Code JLCC-28 / CQCC28 —
Erasure Method Ultraviolet (UV) via top window —
Programming Altera Logic Programmer compatible —
Temperature na Operasyon -40C to +85C (industrial, per EP610 family suffix convention) 0 C to +70 C (commercial) / -55 C to +125 C (military)
Uri ng Pagpapasok Surface Mount (JLCC) Through-Hole
Tindminan RoHS [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Macro Cells — 16
Logic Gates — Equivalent to 300 gates (typical)
Pin-to-Pin Delay (tPD) — 30 ns
Supply Voltage (VCC) — 4.75 V to 5.25 V
Programming Voltage (VPP) — 13 V nominal
Technology — CMOS EPROM (UV-erasable)
Erase/Program Cycles — 1000 typical
Type ng Output — CMOS tri-state (programmable)
Logic Compatibility — TTL and CMOS
Turbo Mode — Yes (registered path bypass)

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