EP610LI-35 vs EP610JI-30 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP610LI-35 sa pamamagitan ng Altera at EP610JI-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP610LI-35 EP610JI-30
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Classic EPLD Altera Classic EPLD (EP610)
Series EP610 —
Number of Macrocells 16 —
Usable Gates 300 —
Number of I/O Pins 16 —
Total Inputs 20 —
Dedicated Inputs 4 4
External Clock Inputs 2 —
Product Terms 160 160
Maximum Propagation Delay 35 ns (tpd) —
Maximum Operating Frequency 28.6 MHz (fmax) —
Pipelined Data Rate Up to 100 MHz Up to 100 MHz
Volte ng Pagbibigay 5 V 5 V (single supply)
Process Technology CMOS CMOS
Architecture PAL-type (AND-OR array) —
Packhaging 28-pin PLCC (windowed ceramic, 'LI') CQCC28 (windowed ceramic JLCC, J-bend)
Hanay ng Temperature na Operasyon [DATA_NEEDED: military/industrial operating temperature range] —
Programming Technology UV-erasable (EPROM) —
Uri ng Pagpapasok Surface Mount Surface Mount (JLCC)
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status - vintage ceramic package, likely non-RoHS]
Device Type — UV Erasable Programmable Logic Device (EPLD)
Macrocells — 16
Propagation Delay (tpd) — 30 ns (max)
I/O Pins — 16
External Clocks — 2
Package Code — JLCC-28 / CQCC28
Erasure Method — Ultraviolet (UV) via top window
Programming — Altera Logic Programmer compatible
Temperature na Operasyon — -40C to +85C (industrial, per EP610 family suffix convention)
Lead-Free — [DATA_NEEDED: lead-free status]

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