EP610PC-25T vs EP610PC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP610PC-25T sa pamamagitan ng Intel at EP610PC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EP610PC-25T - 16-Macrocell Classic EPLD, 25ns, PDIP-24 | Intel / Altera
EP610PC-25T ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EP610PC-25T | EP610PC-15 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Manufacturer | Intel (formerly Altera) | — |
| Distributor / Stocking Source | Rochester Electronics, LLC | — |
| Device Family | Altera Classic EPLD - EP610 | — |
| Device Type | Erasable Programmable Logic Device (EPLD, OTP for plastic package) | EPLD (Erasable Programmable Logic Device) |
| Logic Capacity | 300 usable gates | — |
| Macro Cells | 16 | — |
| Registers | 16 | — |
| User I/Os | 16 | — |
| Propagation Delay (tPD) | 25 ns (speed grade 25) | — |
| Maximum Toggle Frequency | [DATA_NEEDED: max fmax] | — |
| Pipelined Data Rate | up to 100 MHz | Up to 100 MHz |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Process Technology | ECMOS (CMOS, EPROM-based) | — |
| Packhaging | PDIP-24 (Plastic DIP, 24-pin, 0.300 in row spacing) | PDIP-24 (plastic DIP, 24-pin) |
| Pinout Compatibility | Pin-compatible with EP610DC-25 (CERDIP-24, windowed) | — |
| Temperature na Operasyon | 0 °C to +70 °C (commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Method | OTP (one-time programmable) via Altera programming hardware | — |
| Uri ng Pagpapasok | Through-hole | Through-Hole (DIP) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Shipping Form (T suffix) | Tube | — |
| Family | — | Classic EPLD |
| Usable Gates | — | 300 gates |
| Macrocells | — | 16 |
| Logic Delay (tPD) | — | 15 ns (pin-to-pin, -15 speed grade) |
| Maximum Counter Frequency | — | 100 MHz (per family datasheet) |
| Technology | — | CMOS |
| Architecture | — | PAL-type, sum-of-products AND/OR array |
| TTL Emulation | — | 100% TTL compatible |
| Bilang ng Pin | — | 24 pins |
| Development Tool | — | Altera MAX+PLUS II |
| Logic Test Circuitry | — | On-board for AC/DC verification |