EP910DI-30 vs EP910DC-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DI-30 sa pamamagitan ng Rochester Electronics at EP910DC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 NrndPagsanggunian na paghahambing
| Parametro | EP910DI-30 | EP910DC-35 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | — |
| Family | Classic EPLD (Altera EP910 series) | Classic EPLD EP910 |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | 35 ns |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM cell |
| Packhaging | CDIP-40 (ceramic DIP, 40-pin with UV window) | 40-pin CDIP (Ceramic DIP) with quartz window |
| Uri ng Pagpapasok | Through-Hole (DIP) | — |
| Dedicated Inputs | 10 | 12 |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| Bilang ng Pin | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | 0 °C to +70 °C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | Non-compliant (ceramic DIP with Pb-bearing lead finish) |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Device Type | — | UV-Erasable CMOS PLD (PAL-type) |
| Architecture | — | PAL-type sum-of-products AND-OR array |
| Usable Gates | — | 900 gates |
| Macrocells | — | 24 |
| Product Terms | — | 240 |
| I/O Pins | — | 24 |
| Total Inputs | — | 36 |
| Maksimum na Taktiko ng Oras | — | 37 MHz (typical, internal) |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V (5 V nominal) |
| Lead Pitch | — | 2.540 mm |
| Termination Style | — | Through-Hole |
| Programming Method | — | JEDEC fuse map via device programmer; UV erase |
| Lifecycle | — | Obsolete / last-time-buy from authorized distributors |