EP910DI-30 vs EP910DM-40 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910DI-30 sa pamamagitan ng Rochester Electronics at EP910DM-40 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Rochester Electronics
EP910DI-30 - 24-Macrocell EPLD, 30ns, CDIP-40 | Altera (Rochester)
EP910DI-30 Nrnd
Pagsanggunian na paghahambing
| Parametro | EP910DI-30 | EP910DM-40 |
|---|---|---|
| Brand | Rochester Electronics | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Product Type | UV-Erasable Programmable Logic Device (EPLD) | UV Erasable Programmable Logic Device (EPLD) |
| Family | Classic EPLD (Altera EP910 series) | Altera Classic EP910 |
| Macrocell Count | 24 | — |
| Propagation Delay (tpd) | 30 ns | — |
| Maximum Toggle Frequency (fmax) | 62 MHz | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Technology | CMOS, UV-erasable EPROM | — |
| Packhaging | CDIP-40 (ceramic DIP, 40-pin with UV window) | 40-pin Ceramic DIP (Cerdip) with UV window |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole (DIP) |
| Dedicated Inputs | 10 | 36 |
| Dedicated I/O Pins | 12 (12 input + 12 output) | — |
| Output Enable Pins | 2 | — |
| Bilang ng Pin | 40 | — |
| Programmable Logic Element | JEDEC fuse map (3rd-party programmer) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS compliance status] |
| Manufacturer (Original) | Altera (now Intel PSG) | — |
| Current Distributor / Authorized Aftermarket | Rochester Electronics, LLC | — |
| Architecture | — | PAL-type AND/OR with global programmable interconnect bus |
| Macrocells | — | 24 |
| Dedicated Outputs | — | 24 |
| Bidirectional I/O Lines | — | 24 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 40 ns |
| External Clocks | — | 2 |
| Process Technology | — | CMOS |
| Volte ng Pagbibigay | — | 5 V |
| Programming Interface | — | JEDEC-standard fuse-map / UV erasure |