EP910ILC-15N vs EP910ILC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-15N sa pamamagitan ng Altera at EP910ILC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete
Pagsanggunian na paghahambing
| Parametro | EP910ILC-15N | EP910ILC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic | EP910 Classic EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 450 | — |
| Macro Cells | 24 | — |
| Maximum Propagation Delay (tPD) | 15 ns | — |
| Maximum Operating Frequency | 66.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| User I/O Pins | 36 | 36 |
| Dedicated Input Pins | 16 | — |
| Packhaging | PLCC-44 (J-lead, surface mount) | 44-pin JLCC (windowed ceramic) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0 C to +70 C (commercial) | -40C to +85C (industrial) |
| Process Technology | CMOS EPROM (one-time programmable) | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| Tindminan RoHS | Compliant | non_compliant (ceramic windowed package) |
| Programming | EPROM / JTAG (Classic EP-series) | — |
| Macrocells | — | 24 |
| Propagation Delay (tPD) | — | 25 ns |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Technology | — | CMOS EPROM (UV-erasable) |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| Volte ng Pagbibigay | — | 5 V |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Katayuan ng Lifecycle | — | Obsolete - last time buy was late 1990s |