EP910ILC-25 vs EP910ILC-15N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILC-25 sa pamamagitan ng Intel at EP910ILC-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N ObsoletePagsanggunian na paghahambing
| Parametro | EP910ILC-25 | EP910ILC-15N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | EP910 Classic EPLD | Classic |
| Macrocells | 24 | — |
| User I/O Pins | 36 | 36 |
| Propagation Delay (tPD) | 25 ns | — |
| Internal Frequency (fMAX) | [DATA_NEEDED: fMAX rating] | — |
| Logic Blocks | Sum-of-products AND/OR array | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Configuration Memory | Non-volatile EPROM (windowed ceramic) | — |
| Packhaging | 44-pin JLCC (windowed ceramic) | PLCC-44 (J-lead, surface mount) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | -40C to +85C (industrial) | 0 C to +70 C (commercial) |
| Volte ng Pagbibigay | 5 V | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Tindminan RoHS | non_compliant (ceramic windowed package) | Compliant |
| Katayuan ng Lifecycle | Obsolete - last time buy was late 1990s | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 450 |
| Macro Cells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 66.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Dedicated Input Pins | — | 16 |
| Process Technology | — | CMOS EPROM (one-time programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming | — | EPROM / JTAG (Classic EP-series) |