EP910ILI-25 vs EP910ILC-15N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910ILI-25 sa pamamagitan ng Altera at EP910ILC-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N ObsoletePagsanggunian na paghahambing
| Parametro | EP910ILI-25 | EP910ILC-15N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Series | EP910 (Classic EPLD) | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 (maximum) | — |
| Propagation Delay (tPD) | 25 ns | — |
| Technology | CMOS, EPROM | — |
| Architecture | PAL-type with global interconnect bus | — |
| Packhaging | PLCC-44 (windowed ceramic, J-lead) | PLCC-44 (J-lead, surface mount) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | 0 C to +70 C (commercial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | — |
| Logic Test Circuitry | On-board JTAG-compatible test | — |
| Tindminan RoHS | Non-compliant (windowed ceramic package) | Compliant |
| Family | — | Classic |
| Logic Gates | — | 450 |
| Macro Cells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 66.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | — | 36 |
| Dedicated Input Pins | — | 16 |
| Uri ng Pagpapasok | — | Surface Mount |
| Process Technology | — | CMOS EPROM (one-time programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming | — | EPROM / JTAG (Classic EP-series) |