EP910ILI-25 vs EP910ILC-15N 比較
詳細並排比較 EP910ILI-25 由 Altera 與 EP910ILC-15N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EP910ILC-15N - 450 Gate 24-Macrocell Classic CPLD, 15ns, 5V, 44-PLCC | Altera
EP910ILC-15N Obsolete規格比較
| 參數 | EP910ILI-25 | EP910ILC-15N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Series | EP910 (Classic EPLD) | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Product Terms | 240 (maximum) | — |
| Propagation Delay (tPD) | 25 ns | — |
| Technology | CMOS, EPROM | — |
| Architecture | PAL-type with global interconnect bus | — |
| 封裝 | PLCC-44 (windowed ceramic, J-lead) | PLCC-44 (J-lead, surface mount) |
| Operating Voltage | 5 V (4.75 V to 5.25 V) | — |
| 工作溫度 | -40C to +85C (Industrial) | 0 C to +70 C (commercial) |
| Programming Method | UV-erasable (windowed), MAX+PLUS II programmer | — |
| Logic Test Circuitry | On-board JTAG-compatible test | — |
| RoHS 狀態 | Non-compliant (windowed ceramic package) | Compliant |
| Family | — | Classic |
| Logic Gates | — | 450 |
| Macro Cells | — | 24 |
| Maximum Propagation Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 66.6 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| User I/O Pins | — | 36 |
| Dedicated Input Pins | — | 16 |
| 安裝類型 | — | Surface Mount |
| Process Technology | — | CMOS EPROM (one-time programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Programming | — | EPROM / JTAG (Classic EP-series) |