EP910IPC-12 vs EP910IDC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910IPC-12 sa pamamagitan ng Altera at EP910IDC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910IPC-12 | EP910IDC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Classic EPLD | Classic EPLD |
| Macrocells | 24 | 24 |
| Usable Gates | 450 | — |
| Maximum Operating Frequency (fMAX) | 76.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 12 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | 5 V |
| Dedicated Inputs | 10 | 10 |
| I/O Pins | 24 | 24 |
| Packhaging | 40-pin PDIP | 40-pin CDIP (Ceramic DIP, through-hole) |
| Uri ng Pagpapasok | Through Hole | — |
| Technology | CMOS EPLD (UV-erasable or OTP) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | — |
| Programming Toolchain | MAX+PLUS II | — |
| Logic Capacity | Equivalent to ~24 PAL16V8s | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | non_compliant (ceramic DIP contains lead) |
| Manufacturer | — | Altera (now Intel PSG) |
| Equivalent Gates | — | 450 |
| Flip-Flops | — | 48 |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Maximum Frequency (fCNT) | — | 66.6 MHz |
| Terminal Count | — | 40 |
| Terminal Form | — | Through-Hole |
| Temperature Grade | — | Commercial (0C to +70C) |
| Programmable Security Bit | — | Yes |
| On-board Test Circuitry | — | Yes |
| Logic Type | — | UV Erasable EPROM-based |
| Programming Technology | — | EPROM (UV-erasable) |