EP910LC-35 vs EP910LC-35H Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-35 sa pamamagitan ng Altera at EP910LC-35H sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC-35 | EP910LC-35H |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic (EP910) | Classic EPLD (EP910) |
| Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Maximum Toggle Frequency | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V | 5 V (4.75 V to 5.25 V) |
| Technology | CMOS EPROM | CMOS, UV-erasable EPROM |
| Packhaging | PLCC-44 (J-lead, LC suffix) | 40-pin Ceramic DIP (H suffix) |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range grade] |
| Bilang ng Pin | 44 | — |
| Programmable Flip-Flops | Yes (per macrocell) | — |
| Output Enable Control | Per macrocell | — |
| Erasure Method | UV (windowed) or OTP (plastic) | UV (quartz window on H package) |
| Tindminan RoHS | Not applicable (legacy product) | unknown |
| Logic Elements | — | 24 macrocells |
| Equivalent Gates | — | 450 usable gates |
| Propagation Delay (tpd) | — | 35 ns |
| User I/O Pins | — | 36 |
| Dedicated Inputs | — | 10 |
| Programming Method | — | Altera hardware programmer |
| Logic Levels | — | TTL compatible |
| Kuru-kuryente ng Kapayapaan | — | [DATA_NEEDED: typical ICC value] |
| Process Node | — | [DATA_NEEDED: process geometry] |
| Uri ng Pagpapasok | — | Through-hole (Ceramic DIP) |
| Lifecycle | — | Obsolete (long-term supply via Rochester Electronics) |