EP910LC-35H vs EP910LC-40H Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-35H sa pamamagitan ng Altera at EP910LC-40H sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LC-35H EP910LC-40H
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Classic EPLD (EP910) Classic EPLD (EP910)
Logic Elements 24 macrocells 24 macro cells / expandable to 48 via expander terms
Equivalent Gates 450 usable gates —
Propagation Delay (tpd) 35 ns —
Supply Voltage (VCC) 5 V (4.75 V to 5.25 V) 4.75 V to 5.25 V (5 V nominal)
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM
Packhaging 40-pin Ceramic DIP (H suffix) 40-pin Ceramic DIP (CDIP-40), JEDEC standard
User I/O Pins 36 —
Dedicated Inputs 10 —
Temperature na Operasyon [DATA_NEEDED: operating temperature range grade] -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade]
Erasure Method UV (quartz window on H package) —
Programming Method Altera hardware programmer UV-erase + EPROM program, ~100 erase cycles
Logic Levels TTL compatible —
Kuru-kuryente ng Kapayapaan [DATA_NEEDED: typical ICC value] —
Process Node [DATA_NEEDED: process geometry] —
Uri ng Pagpapasok Through-hole (Ceramic DIP) Through-Hole (THT)
Tindminan RoHS unknown [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP]
Lifecycle Obsolete (long-term supply via Rochester Electronics) —
Macro Cells — 24
Usable Gates — 450
Propagation Delay (tPD) — 40 ns max
Supply Current (ICC) — Low-power CMOS, typical ICC < 100 mA
Speed Grade — -40 (40 ns tPD)
I/O Pins — [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical]

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita