EP910LC-35H vs EP910LI-35H Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-35H sa pamamagitan ng Altera at EP910LI-35H sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC-35H | EP910LI-35H |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Classic EPLD (EP910) | Altera Classic EPLD (EP910) |
| Logic Elements | 24 macrocells | — |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (±10%) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM cell |
| Packhaging | 40-pin Ceramic DIP (H suffix) | 44-pin PLCC (J-lead) |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 10 | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range grade] | -40C to +85C (industrial) |
| Erasure Method | UV (quartz window on H package) | — |
| Programming Method | Altera hardware programmer | — |
| Logic Levels | TTL compatible | — |
| Kuru-kuryente ng Kapayapaan | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| Uri ng Pagpapasok | Through-hole (Ceramic DIP) | Surface Mount |
| Tindminan RoHS | unknown | unknown |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | — |
| Logic Capacity | — | 900 usable gates |
| Macro Cells | — | 24 |
| Speed Grade (tPD) | — | 35 ns |
| Maximum Frequency | — | [DATA_NEEDED: fMAX] |
| Standby Current | — | [DATA_NEEDED: ICCSB] |
| Active Supply Current | — | [DATA_NEEDED: ICC] |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Lead-Free Option (H suffix) | — | Yes (H suffix) |