EP910LC-35H vs EP910LI-35H 比較
詳細並排比較 EP910LC-35H 由 Altera 與 EP910LI-35H 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-35H | EP910LI-35H |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Classic EPLD (EP910) | Altera Classic EPLD (EP910) |
| Logic Elements | 24 macrocells | — |
| Equivalent Gates | 450 usable gates | — |
| Propagation Delay (tpd) | 35 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V (±10%) |
| Technology | CMOS, UV-erasable EPROM | CMOS, UV-erasable EPROM cell |
| 封裝 | 40-pin Ceramic DIP (H suffix) | 44-pin PLCC (J-lead) |
| User I/O Pins | 36 | — |
| Dedicated Inputs | 10 | — |
| 工作溫度 | [DATA_NEEDED: operating temperature range grade] | -40C to +85C (industrial) |
| Erasure Method | UV (quartz window on H package) | — |
| Programming Method | Altera hardware programmer | — |
| Logic Levels | TTL compatible | — |
| 靜態電流 | [DATA_NEEDED: typical ICC value] | — |
| Process Node | [DATA_NEEDED: process geometry] | — |
| 安裝類型 | Through-hole (Ceramic DIP) | Surface Mount |
| RoHS 狀態 | unknown | unknown |
| Lifecycle | Obsolete (long-term supply via Rochester Electronics) | — |
| Logic Capacity | — | 900 usable gates |
| Macro Cells | — | 24 |
| Speed Grade (tPD) | — | 35 ns |
| Maximum Frequency | — | [DATA_NEEDED: fMAX] |
| Standby Current | — | [DATA_NEEDED: ICCSB] |
| Active Supply Current | — | [DATA_NEEDED: ICC] |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Lead-Free Option (H suffix) | — | Yes (H suffix) |