EP910LC-40 vs EP910LC-40H Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-40 sa pamamagitan ng Rochester Electronics at EP910LC-40H sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LC-40 EP910LC-40H
Brand Rochester Electronics Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Manufacturer Rochester Electronics (Altera original) —
Device Family Altera Classic EPLD - EP910 —
Product Type EPLD (Erasable Programmable Logic Device) —
Usable Gates 450 450
Macrocells 24 —
Logic Array Blocks 2 (12 macrocells each) —
Propagation Delay (tPD) 40 ns 40 ns max
Maximum Toggle Frequency (fMAX) 25 MHz —
User I/O Pins 36 —
Dedicated Inputs 4 —
Supply Voltage (VCC) 5 V (single supply) 4.75 V to 5.25 V (5 V nominal)
Technology CMOS EPROM CMOS, UV-erasable EPROM
Packhaging PQCC-44 (Plastic Leaded Chip Carrier, J-lead) 40-pin Ceramic DIP (CDIP-40), JEDEC standard
Operating Temperature (Commercial) 0 C to +70 C —
Programming Method Altera Logic Programmer (PLAD-J), 4-wire serial UV-erase + EPROM program, ~100 erase cycles
Tindminan RoHS Not applicable (legacy) [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP]
Lead-Free Status Not applicable —
Family — Classic EPLD (EP910)
Macro Cells — 24
Logic Elements — 24 macro cells / expandable to 48 via expander terms
Supply Current (ICC) — Low-power CMOS, typical ICC < 100 mA
Uri ng Pagpapasok — Through-Hole (THT)
Temperature na Operasyon — -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade]
Speed Grade — -40 (40 ns tPD)
I/O Pins — [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical]

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