EP910LC-40H vs EP910LC-35H Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-40H sa pamamagitan ng Altera at EP910LC-35H sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LC-40H EP910LC-35H
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Classic EPLD (EP910) Classic EPLD (EP910)
Macro Cells 24 —
Usable Gates 450 —
Logic Elements 24 macro cells / expandable to 48 via expander terms 24 macrocells
Propagation Delay (tPD) 40 ns max —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (4.75 V to 5.25 V)
Supply Current (ICC) Low-power CMOS, typical ICC < 100 mA —
Technology CMOS, UV-erasable EPROM CMOS, UV-erasable EPROM
Packhaging 40-pin Ceramic DIP (CDIP-40), JEDEC standard 40-pin Ceramic DIP (H suffix)
Uri ng Pagpapasok Through-Hole (THT) Through-hole (Ceramic DIP)
Temperature na Operasyon -40C to +85C (industrial) [DATA_NEEDED: confirm exact temp grade] [DATA_NEEDED: operating temperature range grade]
Speed Grade -40 (40 ns tPD) —
Programming Method UV-erase + EPROM program, ~100 erase cycles Altera hardware programmer
I/O Pins [DATA_NEEDED: I/O count - datasheet indicates 36 user I/O typical] —
Tindminan RoHS [DATA_NEEDED: not confirmed from datasheet - non-RoHS likely given vintage ceramic DIP] unknown
Equivalent Gates — 450 usable gates
Propagation Delay (tpd) — 35 ns
User I/O Pins — 36
Dedicated Inputs — 10
Erasure Method — UV (quartz window on H package)
Logic Levels — TTL compatible
Kuru-kuryente ng Kapayapaan — [DATA_NEEDED: typical ICC value]
Process Node — [DATA_NEEDED: process geometry]
Lifecycle — Obsolete (long-term supply via Rochester Electronics)

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