EP910LC-40T vs EP910LI-40T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC-40T sa pamamagitan ng Altera at EP910LI-40T sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC-40T | EP910LI-40T |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | Altera Classic EPLD | Classic EPLD |
| Equivalent Gates | 450 gates | — |
| Macrocells | 24 | 24 |
| Logic Array Blocks | 4 Logic Expandable AND-OR arrays | — |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Maximum Frequency (fMAX) | 25 MHz | — |
| Volte ng Pagbibigay | 5 V (4.75 V to 5.25 V) | 5 V (typical) |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable EPROM |
| Packhaging | PLCC-44 (PQCC44) | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC |
| Temperature na Operasyon | -40 C to +85 C (commercial, per -LC suffix family) | -40C to +85C (Industrial) |
| Programming | Altera MAX+PLUS II / APLUS tools | — |
| Erase/Reprogram Cycles | 100 (windowed UV-erase family) | — |
| Bilang ng Pin | 44 | — |
| Packaging Option | Tape and Reel (T suffix) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - not stated in web data] | [DATA_NEEDED: rohs status] |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Maximum Inputs | — | 36 |
| Maximum Outputs | — | 24 |
| Product Terms | — | 240 |
| Architecture | — | PAL-type with global bus |
| Programming Method | — | Altera Master Programming Unit (MPU), no JTAG |