EP910LC-40T vs EP910LI-40T 比較
詳細並排比較 EP910LC-40T 由 Altera 與 EP910LI-40T 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LC-40T | EP910LI-40T |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Family | Altera Classic EPLD | Classic EPLD |
| Equivalent Gates | 450 gates | — |
| Macrocells | 24 | 24 |
| Logic Array Blocks | 4 Logic Expandable AND-OR arrays | — |
| User I/O Pins | 36 | — |
| Propagation Delay (tPD) | 40 ns | 40 ns |
| Maximum Frequency (fMAX) | 25 MHz | — |
| 供應電壓 | 5 V (4.75 V to 5.25 V) | 5 V (typical) |
| Technology | CMOS, UV-erasable | CMOS, UV-erasable EPROM |
| 封裝 | PLCC-44 (PQCC44) | Tape and Reel (suffix T); 40-pin DIP / 44-pin PLCC |
| 工作溫度 | -40 C to +85 C (commercial, per -LC suffix family) | -40C to +85C (Industrial) |
| Programming | Altera MAX+PLUS II / APLUS tools | — |
| Erase/Reprogram Cycles | 100 (windowed UV-erase family) | — |
| 腳位數 | 44 | — |
| Packaging Option | Tape and Reel (T suffix) | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status - not stated in web data] | [DATA_NEEDED: rohs status] |
| Dedicated Inputs | — | 12 |
| I/O Pins | — | 24 |
| Maximum Inputs | — | 36 |
| Maximum Outputs | — | 24 |
| Product Terms | — | 240 |
| Architecture | — | PAL-type with global bus |
| Programming Method | — | Altera Master Programming Unit (MPU), no JTAG |