EP910LC44-35 vs EP910LI44-35 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LC44-35 sa pamamagitan ng Intel at EP910LI44-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LC44-35 | EP910LI44-35 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Family | Classic EPLD (OT sub-family) | — |
| Architecture | PAL-type AND/OR array | PAL-type macrocell (EPLD) |
| Macrocells | 24 | — |
| Usable Gates | 450 | — |
| Propagation Delay (tPD) | 35 ns (max) | 35 ns |
| Maximum Frequency (fMAX) | 28.6 MHz | — |
| Total Inputs | 36 | — |
| I/O Pins | 24 | — |
| Global Clocks | 2 | — |
| Supply Voltage (VCC) | 5 V (single supply) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: temperature grade] |
| Packhaging | 44-pin PLCC (J-leaded) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount / Through-Hole Socket |
| Process Technology | CMOS | CMOS |
| Programmability | UV-erasable (windowed ceramic) | UV-erasable / one-time programmable |
| Device Family | — | Altera Classic EPLD |
| Series | — | EP910 |
| Number of Macrocells | — | 24 |
| Number of External Clocks | — | 2 |
| Maksimum na Taktiko ng Oras | — | 37 MHz |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC range] |
| Bilang ng Pins | — | 44 |
| Package Type | — | PLCC-44 (J-lead) |
| Tindminan RoHS | — | unknown |
| Logic Family | — | Classic EPLD |