EP910LI-35 vs EP910ILC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-35 sa pamamagitan ng Altera at EP910ILC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-35 | EP910ILC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | Altera Classic EPLD | EP910 Classic EPLD |
| Device Series | EP910 | — |
| Usable Gates | 900 | — |
| Macrocells | 24 | 24 |
| Maximum User I/O Pins | 38 | — |
| Propagation Delay (t_PD) | 35 ns | — |
| Maximum Counter Frequency (f_CNT) | 76.9 MHz | — |
| Volte ng Pagbibigay | 5 V (4.75 V to 5.25 V) | 5 V |
| Temperature na Operasyon | -40 °C to +85 °C (Industrial) | -40C to +85C (industrial) |
| Packhaging | 44-pin PLCC (J-lead) | 44-pin JLCC (windowed ceramic) |
| Process Technology | CMOS EPROM | — |
| Programming Technology | EPROM (UV-erasable) | — |
| Erase/Program Cycles | ≥100 | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Lead Pitch | 1.27 mm | — |
| User I/O Pins | — | 36 |
| Propagation Delay (tPD) | — | 25 ns |
| Internal Frequency (fMAX) | — | [DATA_NEEDED: fMAX rating] |
| Logic Blocks | — | Sum-of-products AND/OR array |
| Technology | — | CMOS EPROM (UV-erasable) |
| Configuration Memory | — | Non-volatile EPROM (windowed ceramic) |
| Development Tool | — | Altera MAX+PLUS II (legacy) |
| Tindminan RoHS | — | non_compliant (ceramic windowed package) |
| Katayuan ng Lifecycle | — | Obsolete - last time buy was late 1990s |