EP910LI-40 vs EP910LI-50 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI-40 sa pamamagitan ng Altera at EP910LI-50 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910LI-40 | EP910LI-50 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Manufacturer | Altera (now Intel PSG) | — |
| Product Family | Classic EPLD - EP910 series | — |
| Device Type | Erasable Programmable Logic Device (EPLD) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 bidirectional | [DATA_NEEDED: I/O pin count] |
| Maximum Logic Inputs | 36 | — |
| Product Terms | 240 | — |
| Propagation Delay (tPD) | 40 ns | 50 ns |
| Technology | Low-power CMOS (L-suffix) | CMOS, UV-erasable EPROM |
| Temperature na Operasyon | -40C to +85C (industrial, I-suffix) | -40C to +85C (industrial) |
| Packhaging | PLCC-44 (J-lead, windowed ceramic) | — |
| Uri ng Pagpapasok | Surface Mount (socket-compatible) | — |
| Programmability | UV-erasable, JEDEC-standard algorithm | — |
| Tindminan RoHS | Non-compliant (windowed ceramic PLCC, legacy) | [DATA_NEEDED: RoHS status] |
| Lifecycle | Obsolete - replaced by MAX 7000 / MAX II CPLD family | — |
| Family | — | Altera Classic EPLD |
| Usable Gates | — | 450 |
| Package Type | — | CERDIP-40 (L) |
| Package Pin Count | — | 40 |
| Supply Voltage (VCC) | — | 5 V +/- 10% |
| Logic Blocks | — | Classic AND/OR array architecture |
| Programming Method | — | EPROM programmer (UV-erasable window) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Speed Grade Suffix | — | -50 (50 ns tPD) |