EP910LI44 vs EP910LI44-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910LI44 sa pamamagitan ng Altera at EP910LI44-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910LI44 EP910LI44-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family Classic EPLD —
Architecture PAL-type, CMOS, One-Time-Programmable PAL-type macrocell (EPLD)
Macrocells 24 —
Package Type PLCC-44 (J-lead, surface mount) PLCC-44 (J-lead)
Total Pins 44 —
Dedicated Inputs 12 —
Bidirectional I/O 24 —
Maximum Logic Inputs 36 —
Maximum Outputs 24 —
Flip-Flops 24 —
External Clocks 2 —
Maximum Propagation Delay [DATA_NEEDED: tpd for unmarked speed grade; speed-grade suffix encodes value: -15 = 15 ns, -20 = 20 ns, -25 = 25 ns, -30 = 30 ns, -35 = 35 ns, -40 = 40 ns, -45 = 45 ns, -50 = 50 ns] —
Supply Voltage (VCC) 4.75 V to 5.25 V (commercial), 4.5 V to 5.5 V (industrial) —
Operating Temperature (L grade) -40 °C to +85 °C (industrial) —
Technology CMOS —
Programmability UV-erasable (windowed) or OTP UV-erasable / one-time programmable
Tindminan RoHS non-compliant (original PLCC-44 lead finish) unknown
Uri ng Pagpapasok Surface Mount (PLCC socket compatible) Surface Mount / Through-Hole Socket
Programming Method Altera Logic Programmer card / Data I/O / third-party EPROM programmers —
Device Family — Altera Classic EPLD
Series — EP910
Number of Macrocells — 24
Number of External Clocks — 2
Maksimum na Taktiko ng Oras — 37 MHz
Propagation Delay (tPD) — 35 ns
Process Technology — CMOS
Volte ng Pagbibigay — [DATA_NEEDED: VCC range]
Bilang ng Pins — 44
Temperature na Operasyon — [DATA_NEEDED: temperature grade]
Logic Family — Classic EPLD

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