EP910PC-0 vs EP910PC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-0 sa pamamagitan ng Altera at EP910PC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-0 | EP910PC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | — |
| Family | Classic EPLD | — |
| Usable Gates | 900 gates | 900 |
| Macrocells | 24 | 24 |
| Logic Blocks | 6 (4 macrocells each) | — |
| Dedicated Inputs | 10 | 10 |
| I/O Pins | 24 | — |
| Packhaging | PDIP-40 (Plastic DIP, 40-pin) | PDIP-24 (Plastic DIP) |
| Speed Grade | -0 (slowest) | — |
| Volte ng Pagbibigay | 5 V (single supply) | — |
| Process Technology | CMOS | — |
| Logic Compatibility | 100% TTL emulation | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | UV-erasable / OTP | — |
| Uri ng Pagpapasok | Through-Hole (DIP) | — |
| Product Family | — | Classic EPLD |
| Integration Gates (typical) | — | 4800 |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Maximum Operating Frequency (fMAX) | — | 33.3 MHz |
| Supply Voltage (VCC) | — | 5 V +/- 10% |
| Technology | — | CMOS EPROM |
| Bilang ng Pin | — | 24 |
| Dedicated I/O Pins | — | 12 |
| TTL Compatibility | — | 100% TTL emulation |
| Erasure Method | — | Not erasable in plastic package (windowless) |