EP910PC-20 vs EP910IPC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-20 sa pamamagitan ng Altera at EP910IPC-25 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-20 | EP910IPC-25 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Device | EP910 | — |
| Usable Gates | 900 | 450 |
| Macrocell Count | [DATA_NEEDED: macrocell count] | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| Packhaging | PDIP-24 (PC suffix) | 40-pin PDIP (PDIP-40) |
| Bilang ng Pin | 24 | — |
| Supply Voltage (VCC) | 5 V | 5 V |
| Technology | CMOS EPROM (UV-erasable) | — |
| I/O Compatibility | 100% TTL | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial grade) |
| Programming Method | EPROM programmer, JEDEC fuse map | EPROM cell (OTP / UV erasable) |
| Uri ng Pagpapasok | Through-Hole (DIP) | Through-Hole |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Manufacturer | — | Altera (now Intel) |
| Architecture | — | PAL-type EPLD, CMOS, UV/OTP |
| Macrocells | — | 24 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Frequency (fMAX) | — | 40 MHz |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Development Tool | — | MAX+PLUS II |