EP910PC-20 vs EP910IPC-25 比較
詳細並排比較 EP910PC-20 由 Altera 與 EP910IPC-25 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PC-20 | EP910IPC-25 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Classic EPLD (EP910 series) |
| Device | EP910 | — |
| Usable Gates | 900 | 450 |
| Macrocell Count | [DATA_NEEDED: macrocell count] | — |
| Pin-to-Pin Delay (tPD) | 20 ns | — |
| 封裝 | PDIP-24 (PC suffix) | 40-pin PDIP (PDIP-40) |
| 腳位數 | 24 | — |
| Supply Voltage (VCC) | 5 V | 5 V |
| Technology | CMOS EPROM (UV-erasable) | — |
| I/O Compatibility | 100% TTL | — |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial grade) |
| Programming Method | EPROM programmer, JEDEC fuse map | EPROM cell (OTP / UV erasable) |
| 安裝類型 | Through-Hole (DIP) | Through-Hole |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| Manufacturer | — | Altera (now Intel) |
| Architecture | — | PAL-type EPLD, CMOS, UV/OTP |
| Macrocells | — | 24 |
| Product Terms | — | 240 |
| Propagation Delay (tPD) | — | 25 ns |
| Maximum Frequency (fMAX) | — | 40 MHz |
| Dedicated Inputs | — | 12 |
| Bidirectional I/O Lines | — | 24 |
| Total Inputs (max) | — | 36 |
| Total Outputs (max) | — | 24 |
| Development Tool | — | MAX+PLUS II |