EP910PC-20 vs EP910PC-25 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-20 sa pamamagitan ng Altera at EP910PC-25 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PC-20 | EP910PC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Device | EP910 | — |
| Usable Gates | 900 | 900 |
| Macrocell Count | [DATA_NEEDED: macrocell count] | — |
| Pin-to-Pin Delay (tPD) | 20 ns | 25 ns |
| Packhaging | PDIP-24 (PC suffix) | PDIP-24 (Plastic DIP) |
| Bilang ng Pin | 24 | 24 |
| Supply Voltage (VCC) | 5 V | 5 V +/- 10% |
| Technology | CMOS EPROM (UV-erasable) | CMOS EPROM |
| I/O Compatibility | 100% TTL | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programming Method | EPROM programmer, JEDEC fuse map | — |
| Uri ng Pagpapasok | Through-Hole (DIP) | — |
| Level ng MSL | [DATA_NEEDED: MSL level] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | — |
| Product Family | — | Classic EPLD |
| Integration Gates (typical) | — | 4800 |
| Macrocells | — | 24 |
| Maximum Operating Frequency (fMAX) | — | 33.3 MHz |
| Dedicated Inputs | — | 10 |
| Dedicated I/O Pins | — | 12 |
| TTL Compatibility | — | 100% TTL emulation |
| Erasure Method | — | Not erasable in plastic package (windowless) |