EP910PC-30 vs EP910PC-15T Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PC-30 sa pamamagitan ng Altera at EP910PC-15T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PC-30 EP910PC-15T
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family Altera Classic EPLD Altera Classic EPLD
Macrocells 24 —
Usable Gates ~450 —
Pin-to-Pin Propagation Delay (tPD) 30 ns —
Maximum Counter Frequency (fCNT) 33.3 MHz —
Supply Voltage (VCC) 5 V ±10% 5 V (nominal)
Logic Inputs 36 dedicated —
I/O Pins 12 bidirectional —
Logic Array Blocks (LABs) 4 —
Packhaging PDIP-40 (plastic DIP, 0.6 inch) 40-pin PDIP (Plastic DIP)
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C (commercial)
Programming Technology UV-erasable EPROM cell —
TTL Emulation 100% TTL-compatible —
Power Dissipation [DATA_NEEDED: power dissipation mW] —
Tindminan RoHS Non-compliant (contains lead, PDIP package) [DATA_NEEDED: RoHS compliance status]
Uri ng Pagpapasok Through-hole DIP Through-hole (DIP)
Product Type — EPLD (Erasable Programmable Logic Device)
Macrocell Count — 24
Dedicated Input Pins — 10
Pin-to-Pin Delay (tPD) — 15 ns
Speed Grade — -15 (15 ns)
Technology — CMOS, UV-erasable / OTP
Output Drive Current — [DATA_NEEDED: IOL per output]
Logic Capacity — 24 macrocells / 72 product terms (typical Classic architecture)
Programming Method — JEDEC fuse map via Altera LogicMap / MAX+PLUS II
Lead-Free — [DATA_NEEDED: lead-free status]
Security Bit — Yes (design protection)
Tape and Reel — Yes (suffix T)

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