EP910PI-15T vs EP910IPC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-15T sa pamamagitan ng Altera at EP910IPC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-15T | EP910IPC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | Erasable Programmable Logic Device (EPLD) |
| Family | Altera Classic EPLD (EP910 series) | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | 24 |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| Volte ng Pagbibigay | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | 15 ns |
| Technology | CMOS EEPROM (electrically erasable) | — |
| Packhaging | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | PDIP-40 (Plastic DIP, 40-pin) |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial temp range] | 0C to +70C (commercial, IPC suffix) |
| Programming | JEDEC-standard, serial/parallel programmer | — |
| Tindminan RoHS | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | [DATA_NEEDED: rohs status not confirmed in verified data] |
| Device Family | — | Altera Classic EPLD (EP910 series) |
| Architecture | — | PAL-type, CMOS |
| Product Terms | — | 240 |
| External Clocks | — | 2 |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V |
| Process Technology | — | CMOS |
| Programming Method | — | JEDEC fuse map via Altera EPLD programmer |
| Bilang ng Pin | — | 40 |