EP910PI-20 vs EP910JC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-20 sa pamamagitan ng Altera at EP910JC-30 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-20 | EP910JC-30 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | Altera Classic EPLD Family | — |
| Macrocells | 24 | 24 |
| Propagation Delay (tPD) | 20 ns | — |
| Packhaging | PDIP-40 (PI suffix) | 44-pin Windowed Ceramic J-Lead Chip Carrier (CQCC-44 / JLCC-44) |
| Uri ng Pagpapasok | Through-Hole | Surface Mount (socket-mountable) |
| Supply Voltage (VCC) | 5 V (+/- 5%) | — |
| Temperature na Operasyon | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Technology | CMOS EPROM (UV-erasable windowed variants available) | CMOS EPROM, UV-erasable |
| Configuration Method | Non-volatile EPROM (no boot PROM required) | — |
| Dedicated Inputs | 12 | — |
| Bidirectional I/O Pins | 24 | — |
| Maximum Counter Frequency | 125 MHz | — |
| Output Drive Current (IOL) | 24 mA (TTL-compatible) | — |
| Programmable Polarity | Yes (XOR gate per macrocell) | — |
| Macrocell Flip-Flop | Yes (D-type, programmable) | — |
| Power Dissipation | [DATA_NEEDED: typical power dissipation in mW] | — |
| Programming Interface | JEDEC file via Altera programming hardware | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS compliance] |
| MIL-STD-883 Variant | EP910DM/883B (separate part number) | — |
| Family | — | Classic EPLD (MAX-style) |
| Propagation Delay (tpd) | — | 30 ns |
| Maximum Internal Frequency (Fmax) | — | 33.3 MHz |
| Inputs | — | 36 |
| Product Terms | — | 240 |
| Outputs | — | 10 dedicated |
| Supply Voltage (Vcc) | — | 5 V |
| Supply Current (Icc) | — | [DATA_NEEDED: Icc typical / maximum] |
| Logic Blocks | — | 24 macrocells (AND/OR array architecture) |