EP910PI-25 vs EP910PC-30 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-25 sa pamamagitan ng Intel at EP910PC-30 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-25 | EP910PC-30 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | Altera Classic EPLD |
| Device | EP910 | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | 12 bidirectional |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | 30 ns |
| Maximum Clock Frequency (fMAX) | 40 MHz | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V ±10% |
| Process Technology | 5 V CMOS (EPROM-based) | — |
| Packhaging | PDIP-40 (Plastic DIP) | PDIP-40 (plastic DIP, 0.6 inch) |
| Bilang ng Pin | 40 | — |
| Uri ng Pagpapasok | Through-Hole | Through-hole DIP |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmability | UV-erasable (windowed) / one-time-programmable | — |
| Tindminan RoHS | Non-compliant (PDIP package) | Non-compliant (contains lead, PDIP package) |
| Usable Gates | — | ~450 |
| Maximum Counter Frequency (fCNT) | — | 33.3 MHz |
| Logic Inputs | — | 36 dedicated |
| Logic Array Blocks (LABs) | — | 4 |
| Programming Technology | — | UV-erasable EPROM cell |
| TTL Emulation | — | 100% TTL-compatible |
| Power Dissipation | — | [DATA_NEEDED: power dissipation mW] |