EP910PI-25 vs EP910PI-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-25 sa pamamagitan ng Intel at EP910PI-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-25 | EP910PI-20 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | Altera Classic EPLD | — |
| Device | EP910 | — |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 12 |
| I/O Pins | 24 | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 40 MHz | — |
| Supply Voltage (VCC) | 5 V nominal | 5 V (+/- 5%) |
| Process Technology | 5 V CMOS (EPROM-based) | — |
| Packhaging | PDIP-40 (Plastic DIP) | PDIP-40 (PI suffix) |
| Bilang ng Pin | 40 | — |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Temperature na Operasyon | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Programmability | UV-erasable (windowed) / one-time-programmable | — |
| Tindminan RoHS | Non-compliant (PDIP package) | unknown |
| Device Family | — | Altera Classic EPLD Family |
| Propagation Delay (tPD) | — | 20 ns |
| Technology | — | CMOS EPROM (UV-erasable windowed variants available) |
| Configuration Method | — | Non-volatile EPROM (no boot PROM required) |
| Bidirectional I/O Pins | — | 24 |
| Maximum Counter Frequency | — | 125 MHz |
| Output Drive Current (IOL) | — | 24 mA (TTL-compatible) |
| Programmable Polarity | — | Yes (XOR gate per macrocell) |
| Macrocell Flip-Flop | — | Yes (D-type, programmable) |
| Power Dissipation | — | [DATA_NEEDED: typical power dissipation in mW] |
| Programming Interface | — | JEDEC file via Altera programming hardware |
| MIL-STD-883 Variant | — | EP910DM/883B (separate part number) |