EP910PI-30T vs EP910PI-15T Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-30T sa pamamagitan ng Altera at EP910PI-15T sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EP910PI-30T | EP910PI-15T |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Usable Gates | 480 | — |
| Dedicated Inputs | 10 | 12 |
| Propagation Delay (tPD) | 30 ns | 15 ns max (speed grade -15) |
| Register (Clock-to-Output) Delay | 20 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS EEPROM (electrically erasable) |
| Package Type | 40-pin PDIP (ceramic windowed) | — |
| Uri ng Pagpapasok | Through-Hole | Through-Hole |
| Temperature na Operasyon | -40 C to +85 C (industrial) | [DATA_NEEDED: industrial/commercial temp range] |
| Programming | Altera Classic device programmer / MAX+PLUS II flow | JEDEC-standard, serial/parallel programmer |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | — | 24 |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| Volte ng Pagbibigay | — | 4.5 V to 5.5 V (5 V nominal) |
| Packhaging | — | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |