EP910PI-30T vs EP910PI-15T 비교
다음의 상세 나란히 비교: EP910PI-30T 제조: Altera 및 EP910PI-15T 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EP910PI-30T | EP910PI-15T |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | FPGA & CPLD | FPGA & CPLD |
| 수명 주기 상태 | Obsolete | Obsolete |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $10.95 | $10.95 |
| Product Type | EPLD (Erasable Programmable Logic Device) | Classic EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD | Altera Classic EPLD (EP910 series) |
| Macrocells | 24 | 24 |
| Usable Gates | 480 | — |
| Dedicated Inputs | 10 | 12 |
| Propagation Delay (tPD) | 30 ns | 15 ns max (speed grade -15) |
| Register (Clock-to-Output) Delay | 20 ns | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5 V nominal) | — |
| Technology | CMOS, UV-erasable (windowed ceramic) | CMOS EEPROM (electrically erasable) |
| Package Type | 40-pin PDIP (ceramic windowed) | — |
| 실장 유형 | Through-Hole | Through-Hole |
| 동작 온도 | -40 C to +85 C (industrial) | [DATA_NEEDED: industrial/commercial temp range] |
| Programming | Altera Classic device programmer / MAX+PLUS II flow | JEDEC-standard, serial/parallel programmer |
| RoHS 상태 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| I/O Pins | — | 24 |
| Logic Blocks | — | 6 LABs of 4 macrocells each (Classic architecture) |
| 공급 전압 | — | 4.5 V to 5.5 V (5 V nominal) |
| 패키지 | — | 40-pin PDIP (Plastic DIP, R-PDIP-T40) |
| Output Drive Current | — | [DATA_NEEDED: per-pin DC output current, mA] |