EP910PI-30T vs EP910PI-20 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EP910PI-30T sa pamamagitan ng Altera at EP910PI-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EP910PI-30T EP910PI-20
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Product Type EPLD (Erasable Programmable Logic Device) —
Family Altera Classic EPLD —
Macrocells 24 24
Usable Gates 480 —
Dedicated Inputs 10 12
Propagation Delay (tPD) 30 ns 20 ns
Register (Clock-to-Output) Delay 20 ns —
Supply Voltage (VCC) 4.75 V to 5.25 V (5 V nominal) 5 V (+/- 5%)
Technology CMOS, UV-erasable (windowed ceramic) CMOS EPROM (UV-erasable windowed variants available)
Package Type 40-pin PDIP (ceramic windowed) —
Uri ng Pagpapasok Through-Hole Through-Hole
Temperature na Operasyon -40 C to +85 C (industrial) -40C to +85C (industrial)
Programming Altera Classic device programmer / MAX+PLUS II flow —
Tindminan RoHS [DATA_NEEDED: RoHS status] unknown
Lead-Free [DATA_NEEDED: lead-free status] —
Device Family — Altera Classic EPLD Family
Packhaging — PDIP-40 (PI suffix)
Configuration Method — Non-volatile EPROM (no boot PROM required)
Bidirectional I/O Pins — 24
Maximum Counter Frequency — 125 MHz
Output Drive Current (IOL) — 24 mA (TTL-compatible)
Programmable Polarity — Yes (XOR gate per macrocell)
Macrocell Flip-Flop — Yes (D-type, programmable)
Power Dissipation — [DATA_NEEDED: typical power dissipation in mW]
Programming Interface — JEDEC file via Altera programming hardware
MIL-STD-883 Variant — EP910DM/883B (separate part number)

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