EPC1213LC20 vs EPC1213LI20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC1213LC20 sa pamamagitan ng Intel at EPC1213LI20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC1213LC20 | EPC1213LI20 |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | EEPROM | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Uri ng Memory | OTP Configuration PROM (Flash-based) | OTP Configuration PROM (non-volatile) |
| Laki ng Memory | 212 Kbit | 212 Kbit |
| Interface | Serial (Altera FPGA configuration protocol) | — |
| Maximum Configuration Clock | 6 MHz | — |
| Supply Voltage (Core) | 5.0 V | — |
| I/O Voltage Tolerance | 3.3 V / 5.0 V | 3.3 V or 5 V |
| Programmability | One-Time Programmable (OTP) via IEEE 1149.1 JTAG | OTP (one-time programmable) |
| In-System Programmability | Yes (5.0 V and 3.3 V ISP) | — |
| Supported FPGA Families | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX | — |
| Compression Support | Yes (FPGA decompresses bitstream during load) | — |
| Temperature na Operasyon | 0C to +70C (Commercial) | -40C to +85C (industrial) |
| Packhaging | 20-PLCC (J-lead, 9x9 mm) | 20-PLCC (9x9 mm), J-lead |
| Package Code | QCCJ | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status - legacy Altera part] |
| Uri ng Interface | — | Serial (Altera active-serial configuration) |
| Supply Voltage (VCC) | — | 3.3 V / 5 V |
| Bilang ng Pin | — | 20 |
| Compatible FPGA Families | — | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Configuration Mode | — | Active Serial (AS) |
| Internal Oscillator | — | Yes (generates DCLK to FPGA) |
| Cascade Support | — | Yes (nCASC pin for multi-device chains) |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |