EPC1441LC20 vs EPC1441LI20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC1441LC20 sa pamamagitan ng Altera at EPC1441LI20 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC1441LC20 | EPC1441LI20 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | Memory ICs | Memory ICs |
| Katayuan ng Lifecycle | Aktibo | Obsolete |
| Uri ng Memory | OTP configuration PROM | OTP Configuration PROM (PROM) |
| Configuration Memory Capacity | 440 kb | — |
| Configuration Memory Capacity (Alternate Listing) | 400 kbit | — |
| Configuration Interface | Serial | Altera 4-pin serial (DATA, DCLK, nCONFIG, nSTATUS) |
| Configuration Performance | 8 MHz | — |
| Target Device | SRAM-based LUT devices and FPGAs | — |
| Programmability | One-time programmable | — |
| Packhaging | 20-PLCC | 20-pin PLCC (J-lead, 9x9 mm) |
| Package Dimensions | 9 mm x 9 mm | — |
| Package Code | QCCJ | — |
| Package Shape | Square | — |
| Number of Terminals | 20 | — |
| Hanay ng Temperature na Operasyon | 0 °C to 70 °C | — |
| Temperature Grade | Commercial | — |
| Configuration Device Family | EPC14 | — |
| Typical Use | FPGA configuration memory | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| Density | — | 441 kbits (440,800 bits) |
| Number of Words | — | 440,800 |
| Bits per Word | — | 1 bit |
| Supported FPGA Families | — | ACEX, APEX 20K / 20KC / 20KE, FLEX 10KE, FLEX 10KA, Mercury |
| Volte ng Pagbibigay | — | 3.3 V |
| Temperature na Operasyon | — | -40 C to +85 C (industrial) |
| Pin Pitch | — | 1.27 mm |
| Programming Method | — | One-Time-Programmable via Altera programming hardware |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Configuration Time | — | Depends on FPGA bitstream length and DCLK frequency |