EPC22LC20 vs EPC2CC20N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC22LC20 sa pamamagitan ng Intel at EPC2CC20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC22LC20 | EPC2CC20N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Fungsi | In-System Programmable Configuration PROM for SRAM-based FPGAs | Configuration device for SRAM-based LUT FPGAs |
| Laki ng Memory | 1.6 Mbit | — |
| Programmable Type | In System Programmable (IEEE 1532 / Jam STAPL) | — |
| Supply Voltage - Low Range | 3.0 V to 3.6 V | — |
| Supply Voltage - High Range | 4.75 V to 5.25 V | — |
| Supported FPGA Families | ACEX 1K, APEX II, APEX 20K, FLEX 10K | — |
| Configuration Interface | Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) | 16-bit parallel (FPP) / Passive Serial (PS) |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | JTAG (IEEE 1149.1) via ByteBlasterMV / USB-Blaster |
| Packhaging / Kaso | 20-LCC (J-Lead, 9 x 9 mm) | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC-20 socket compatible) |
| Packaging | Tube | — |
| Temperature na Operasyon | 0 C to +70 C (commercial) | [DATA_NEEDED: industrial/commercial temp range] |
| Minimum DC Input Voltage | -0.3 V | — |
| Input Overshoot Tolerance | 7.0 V for <100 mA, <20 ns no-load | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns no-load | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status not in verified data] | — |
| Density | — | [DATA_NEEDED: bitstream density in bits] |
| Packhaging | — | PLCC-20 |
| Supply Voltage (VCC) | — | 3.3 V |
| In-System Programmable | — | Yes |
| Error Detection | — | 16-bit CRC on configuration frames |
| Configuration Modes Supported | — | FPP and PS (depends on host FPGA) |
| Cascadable | — | Yes (multiple EPC2 devices for larger bitstreams) |
| Open-Drain Status Pin | — | Yes (CONF_DONE / nSTATUS compatible) |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance status] |