EPC22LC20 vs EPC2L1696-10F Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC22LC20 sa pamamagitan ng Intel at EPC2L1696-10F sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC22LC20 | EPC2L1696-10F |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Fungsi | In-System Programmable Configuration PROM for SRAM-based FPGAs | — |
| Laki ng Memory | 1.6 Mbit | — |
| Programmable Type | In System Programmable (IEEE 1532 / Jam STAPL) | — |
| Supply Voltage - Low Range | 3.0 V to 3.6 V | — |
| Supply Voltage - High Range | 4.75 V to 5.25 V | — |
| Supported FPGA Families | ACEX 1K, APEX II, APEX 20K, FLEX 10K | — |
| Configuration Interface | Altera serial configuration (DCLK / DATA0 / nSTATUS / CONF_DONE) | 5-pin Altera serial (nCS, DCLK, DATA, OE, nINIT_CONF) |
| Programming Interface | JTAG (IEEE 1149.1 / IEEE 1532) | — |
| Packhaging / Kaso | 20-LCC (J-Lead, 9 x 9 mm) | — |
| Uri ng Pagpapasok | Surface Mount (PLCC socket compatible) | Surface Mount |
| Packaging | Tube | — |
| Temperature na Operasyon | 0 C to +70 C (commercial) | 0C to +70C (commercial) |
| Minimum DC Input Voltage | -0.3 V | — |
| Input Overshoot Tolerance | 7.0 V for <100 mA, <20 ns no-load | — |
| Input Undershoot Tolerance | -2.0 V for <100 mA, <20 ns no-load | — |
| Lead-Free / RoHS | [DATA_NEEDED: lead-free status not in verified data] | — |
| Device Type | — | Configuration EPROM for SRAM-based LUT FPGAs |
| Supported Logic Density | — | 1696 LUTs |
| Memory Technology | — | CMOS EEPROM |
| Supply Voltage (VCC) | — | 3.3 V |
| Access Time | — | 10 ns (speed grade -10) |
| Maximum DCLK Frequency | — | [DATA_NEEDED: DCLK max frequency] |
| Program / Erase Cycles | — | >= 100,000 cycles |
| Data Retention | — | [DATA_NEEDED: data retention years] |
| In-System Programming | — | Yes (4-wire JTAG-style interface) |
| Packhaging | — | 20-pin PLCC |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS status] |