EPC27TC32N vs EPC2TC32N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC27TC32N sa pamamagitan ng Altera at EPC2TC32N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPC27TC32N | EPC2TC32N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | Memory ICs |
| Katayuan ng Lifecycle | Unknown | Obsolete |
| Product Type | Configuration device for SRAM-based LUT devices | — |
| Manufacturer | Altera | Altera (now Intel) |
| Target Logic Type | SRAM-based LUT devices | — |
| Configuration Memory Capacity | [DATA_NEEDED: configuration memory capacity] | — |
| Configuration Interface | [DATA_NEEDED: configuration interface] | — |
| Programming Mode | [DATA_NEEDED: programming mode] | — |
| Supported FPGA Families | [DATA_NEEDED: supported FPGA families] | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Clock Frequency | [DATA_NEEDED: clock frequency] | — |
| Configuration Startup Time | [DATA_NEEDED: configuration startup time] | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature] | 0 °C to +70 °C (Commercial) |
| Packhaging | [DATA_NEEDED: package] | 32-TQFP (7x7 mm) |
| Bilang ng Pin | [DATA_NEEDED: pin count] | — |
| Uri ng Pagpapasok | [DATA_NEEDED: mounting type] | Surface Mount |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Conflict-Mineral Status | [DATA_NEEDED: conflict-mineral status] | — |
| Uri ng Memory | — | Flash Configuration PROM |
| Laki ng Memory | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP) |
| Interface | — | JTAG (IEEE 1149.1) + serial/parallel |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Supply Voltage - VCCIO | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Max Configuration Clock | — | 8 MHz |
| Daisy-Chain Support | — | Yes (multi-FPGA cascade) |
| JTAG Compliance | — | IEEE 1149.1 |
| Configuration Mode | — | Serial (AS) or Parallel (PS/AP) |