EPC27TC32N vs EPC2TC32N 比較
詳細並排比較 EPC27TC32N 由 Altera 與 EPC2TC32N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPC27TC32N | EPC2TC32N |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | Memory ICs |
| 生命週期狀態 | Unknown | Obsolete |
| Product Type | Configuration device for SRAM-based LUT devices | — |
| Manufacturer | Altera | Altera (now Intel) |
| Target Logic Type | SRAM-based LUT devices | — |
| Configuration Memory Capacity | [DATA_NEEDED: configuration memory capacity] | — |
| Configuration Interface | [DATA_NEEDED: configuration interface] | — |
| Programming Mode | [DATA_NEEDED: programming mode] | — |
| Supported FPGA Families | [DATA_NEEDED: supported FPGA families] | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |
| Operating Voltage | [DATA_NEEDED: operating voltage] | — |
| Clock Frequency | [DATA_NEEDED: clock frequency] | — |
| Configuration Startup Time | [DATA_NEEDED: configuration startup time] | — |
| 工作溫度 | [DATA_NEEDED: operating temperature] | 0 °C to +70 °C (Commercial) |
| 封裝 | [DATA_NEEDED: package] | 32-TQFP (7x7 mm) |
| 腳位數 | [DATA_NEEDED: pin count] | — |
| 安裝類型 | [DATA_NEEDED: mounting type] | Surface Mount |
| Package Dimensions | [DATA_NEEDED: package dimensions] | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| REACH Status | [DATA_NEEDED: REACH status] | — |
| AEC-Q100 Qualification | [DATA_NEEDED: AEC-Q100 qualification] | — |
| Lead-Free Status | [DATA_NEEDED: lead-free status] | — |
| Halogen-Free Status | [DATA_NEEDED: halogen-free status] | — |
| Conflict-Mineral Status | [DATA_NEEDED: conflict-mineral status] | — |
| 記憶體類型 | — | Flash Configuration PROM |
| 記憶體容量 | — | 1.6 Mbit |
| Programmable Type | — | In System Programmable (ISP) |
| 介面 | — | JTAG (IEEE 1149.1) + serial/parallel |
| Supply Voltage - VCCINT | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Supply Voltage - VCCIO | — | 3.0 V to 3.6 V or 4.75 V to 5.25 V |
| Max Configuration Clock | — | 8 MHz |
| Daisy-Chain Support | — | Yes (multi-FPGA cascade) |
| JTAG Compliance | — | IEEE 1149.1 |
| Configuration Mode | — | Serial (AS) or Parallel (PS/AP) |