EPC2L120N vs EPC2L20U-HAF480119C Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPC2L120N sa pamamagitan ng Intel at EPC2L20U-HAF480119C sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPC2L20U-HAF480119C - FPGA Config Device, SRAM LUT | Intel
EPC2L20U-HAF480119C ⚠ Huling PagbiliPagsanggunian na paghahambing
| Parametro | EPC2L120N | EPC2L20U-HAF480119C |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | Memory ICs |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Device Type | Configuration Device for SRAM-based LUT FPGAs | — |
| Manufacturer | Intel (formerly Altera) | — |
| Family | EPC2 (Enhanced Configuration Device) | — |
| Memory Capacity | 165,888 bits (400,000 gates equivalent) | — |
| Operating Voltage (VCCIO) | 2.7 V to 3.6 V | — |
| 5V Tolerance | Yes (5V-tolerant I/O) | — |
| Configuration Clock (FPP) | Up to 66 MHz | — |
| Configuration Clock (PS) | Up to 33 MHz | — |
| Internal Oscillator | 8 MHz with programmable divider | — |
| JTAG Interface | IEEE Std 1149.1 compliant, ISP support | — |
| Programming Cycles | 100,000 erase/program cycles | — |
| Sector Erase Time | [DATA_NEEDED: typical sector erase time] | — |
| Packhaging | 84-pin PLCC (J-Lead) | PLCC-20 |
| Configuration Schemes | FPP, PS, JTAG, daisy chain | — |
| Temperature na Operasyon | [DATA_NEEDED: industrial temp range] | — |
| Supported FPGA Families | Cyclone, APEX, FLEX, Mercury, ACEX, Stratix | — |
| Tindminan RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Uri ng Memory | — | Configuration PROM (non-volatile) |
| Laki ng Memory | — | 1.6 Mb |
| Target Device | — | SRAM-based LUT FPGAs (Cyclone, Stratix, APEX families) |
| Core Supply Voltage | — | 3.3 V |
| I/O Tolerance | — | 5 V tolerant |
| Configuration Modes | — | Serial (1-bit), Parallel (8-bit FPP), JTAG |
| JTAG Support | — | Yes (IEEE 1149.1 boundary-scan) |
| Programmability | — | In-system programmable via JTAG |
| Cascade Support | — | Yes (multi-PROM chains for larger FPGAs) |
| Configuration Clock Range | — | 10 MHz to 40 MHz |
| Bitstream Compression Support | — | Yes (Cyclone/Stratix compressed bitstreams) |
| Uri ng Pagpapasok | — | Surface Mount / Socketed |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |