EPC2LC20-U vs EPC2LI20N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LC20-U sa pamamagitan ng Altera at EPC2LI20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC2LC20-U EPC2LI20N
Brand Altera Altera
Kategorya Memory ICs Memory ICs
Katayuan ng Lifecycle Obsolete Obsolete
Uri ng Memory Configuration PROM (Flash, in-system programmable) Non-volatile configuration PROM (Flash)
Laki ng Memory 1.6 Mbit 1.6 Mbit
Interface Serial (4-wire Altera configuration) + JTAG (IEEE 1149.1) —
Max Configuration Clock 10 MHz —
Supply Voltage (VCC) 3.3 V (3.0 V to 3.6 V) —
Programmable In-system via JTAG —
Cascade Support Yes (multi-PROM for larger bitstreams) —
Packhaging 20-PLCC (9x9) —
Uri ng Pagpapasok Surface Mount Surface Mount
Temperature na Operasyon [DATA_NEEDED: full operating temperature range] [DATA_NEEDED: operating temperature range]
Supported FPGA Families ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K —
JTAG Support Yes (IEEE 1149.1 boundary-scan) —
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS status]
Lead-Free [DATA_NEEDED: lead-free status] —
Level ng MSL [DATA_NEEDED: moisture sensitivity level] —
Programmable Type — In System Programmable (ISP via JTAG)
Configuration Mode — Serial
Maximum Configuration Frequency — 10 MHz
Supply Voltage (VCCINT) — 3.0 V to 3.6 V
Supply Voltage (VCCIO) — 4.5 V to 5.5 V
Packhaging / Kaso — 20-PLCC (J-Lead), 9x9 mm
Packaging — Tube
Supported FPGA Series — ACEX 1K, APEX II, Cyclone, Stratix II
JTAG Interface — IEEE 1149.1 boundary scan (TCK/TDI/TMS/TDO)
Configuration Pins — nCS, DCLK, DATA, nCONFIG, nSTATUS, CONF_DONE

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