EPC2LC20N vs EPC2L20N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC2LC20N sa pamamagitan ng Intel at EPC2L20N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC2LC20N EPC2L20N
Brand Intel Altera
Kategorya Memory ICs Memory ICs
Katayuan ng Lifecycle NRND NRND
Fungsi In-System Programmable Configuration PROM for SRAM-based FPGAs In-System Programmable Configuration PROM for SRAM-based LUT FPGAs
Laki ng Memory 1.6 Mbit 1.6 Mbit
Uri ng Memory Flash —
Programmable Type In System Programmable (ISP) In System Programmable (ISP)
Supply Voltage VCCINT 3.0 V to 3.6 V —
Supply Voltage VCCIO 4.75 V to 5.25 V —
Configuration Clock Frequency 8 MHz (max) —
Interface Serial (DATA0, DCLK, nCONFIG, nSTATUS, CONF_DONE) —
JTAG Support IEEE 1149.1 / IEEE 1532 compliant —
Packhaging 20-pin PLCC (J-Lead, 9x9 mm) —
Uri ng Pagpapasok Surface Mount Surface Mount (J-Lead PLCC)
Packaging Tube Tube
Temperature na Operasyon [DATA_NEEDED: operating temperature range] 0C to +70C (commercial)
Supported FPGA Families Altera APEX, Cyclone, Stratix, ACEX, MAX 7000 Altera APEX, ACEX, Cyclone, FLEX 10K, Mercury (per datasheet)
Tindminan RoHS [DATA_NEEDED: RoHS status] Compliant
Supply Voltage - VCCINT/VCCIO — 3.0 V to 3.6 V or 4.5 V to 5.5 V
Packhaging / Kaso — 20-LCC (J-Lead), PLCC-20
Configuration Interface — Serial (Altera FPP / PS configuration scheme)
Cascade Support — Yes (multi-PROM chain via CE control)
Programming Method — In-system via 4-wire ISP / JTAG-style
Bilang ng Pin — 20
Lead Finish — Matte Tin (Pb-free)
Level ng MSL — 3 (168 hours)

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