EPC448PC-20 vs EPC448PC-45A Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC448PC-20 sa pamamagitan ng Altera at EPC448PC-45A sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Altera
EPC448PC-45A EPC448PC-45A - Altera Enhanced Configuration Device | PDIP

EPC448PC-45A - Altera Enhanced Configuration Device | PDIP

EPC448PC-45A ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPC448PC-20 EPC448PC-45A
Brand Altera Altera
Kategorya Memory ICs FPGA & CPLD
Katayuan ng Lifecycle Obsolete Huling Pagbili
Device Family Enhanced Configuration Device (EPC) —
Memory Density 4 Mbit (4,194,304 bits) 4 Mbit (448 Kbit)
Speed Grade -20 -45A
Supply Voltage (VCC) 3.3 V 3.0 V to 3.6 V (3.3 V typical)
Configuration Clock (Max) 20 MHz —
Interface to FPGA Dedicated Altera/Intel configuration serial (Active Serial) —
Programming Interface JTAG (IEEE 1149.1) ISP —
Packhaging 20-ball PC-BGA —
Uri ng Pagpapasok Surface Mount Through-hole (DIP)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] -40 C to +85 C (industrial)
Configuration Time (typical 4 Mbit) Approx. 200 ms at 20 MHz —
Supported FPGA Series APEX 20K, ACEX 1K, Cyclone, Cyclone II/III, Stratix/Stratix II —
Compression Supported (1.5x to 2x depending on bitstream) —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs status from official datasheet]
Lead-Free [DATA_NEEDED: lead-free status] [DATA_NEEDED: lead-free finish status]
Device Type — Enhanced Configuration Device (EPC) for SRAM-based LUT FPGAs
Maximum Access Time — 45 ns
Package Type — Plastic DIP (PDIP-20), 300-mil body
Bilang ng Pin — 20
I/O Voltage Compatibility — 1.8 V, 2.5 V, 3.3 V downstream FPGA
Configuration Interface — Altera Passive Serial (4-wire: nCS, DCLK, DATA, nINIT_CONF)
Programming Technology — EEPROM cell with internal charge pump
Configuration Support — Altera Cyclone, Stratix, APEX, ACEX, Mercury, Excalibur FPGAs
Level ng MSL — Not applicable (through-hole package)

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