EPC80C100T vs EPC40C100 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC80C100T sa pamamagitan ng Intel at EPC40C100 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC80C100T EPC40C100
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Product Type Enhanced Configuration Device for SRAM-based LUT FPGAs —
Manufacturer Intel (formerly Altera) —
Family Enhanced Configuration (EPC) Devices —
Memory Density [DATA_NEEDED: density in Mbit] 40 Mbit
Volte ng Pagbibigay 3.0 V to 3.6 V (3.3 V typical) —
Configuration Modes FPP, PPS, PPA, PS, JTAG —
JTAG Interface IEEE 1149.1 in-system programming —
Internal Oscillator 50 MHz —
Multi-Boot Pages Up to 8 configuration pages —
Page-Mode Read Supported —
In-System Programmability Yes (continuous, via JTAG) —
Packhaging 100-pin PQFP (T = tape and reel) 100-pin EQFP (Enhanced Quad Flat Pack)
Compatible FPGA Families APEX 20K, APEX II, Mercury, ACEX 1K, Cyclone, Stratix —
Temperature na Operasyon -40C to +85C (industrial, [DATA_NEEDED: confirm grade]) —
Tindminan RoHS [DATA_NEEDED: verify from manufacturer page] Compliant
Lead-Free [DATA_NEEDED: verify from manufacturer page] Yes
Device Family — Enhanced Configuration Device
Target FPGAs — Stratix, Cyclone, APEX, Mercury, ACEX families
Configuration Mode — FPP (Fast Passive Parallel) / PS (Passive Serial)
Interface Voltage — 2.5 V / 3.3 V
Maximum FPP Clock Frequency — 66 MHz
Programmability — In-system programmable (JTAG)
Error Detection — Built-in CRC verification
Hanay ng Temperature na Operasyon — -40 C to +85 C (industrial)
Pin Pitch — 0.5 mm
Uri ng Pagpapasok — Surface Mount
Level ng MSL — 3 (168 hours)
Uri ng Memory — NOR Flash

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