EPC8QI100 vs EPC4QI100N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPC8QI100 sa pamamagitan ng Intel at EPC4QI100N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPC8QI100 EPC4QI100N
Brand Intel Altera
Kategorya Memory ICs Memory ICs
Katayuan ng Lifecycle Obsolete Aktibo
Presyo ng Yunit (USD) — $10.40
Uri ng Memory Flash (NOR, Enhanced Configuration PROM) In-System Programmable Configuration PROM (NOR flash)
Laki ng Memory 8 Mbit 4 Mbit (4,194,304 bits)
Supply Voltage (Core) 3.3 V —
Supply Voltage (I/O) 3.3 V —
Interface Altera FPGA configuration serial/parallel (FPP) + JTAG (IEEE 1149.1) Altera serial (x1) configuration + JTAG
In-System Programmability IEEE Std. 1532 compliant —
Programming Language Jam STAPL —
Boundary Scan JTAG boundary-scan test supported —
Data Compression Yes (increases effective capacity) —
Configuration Controller On-chip, dedicated to Altera FPGAs —
Initiate-Configuration Pin nINIT_CONF (private JTAG instruction) —
Temperature na Operasyon -40C to +85C (industrial) -40C to +85C (industrial)
Packhaging 100-PQFP (20 x 14 mm) 100-pin PQFP (PowerPQFP, 20x14 mm)
Uri ng Pagpapasok Surface Mount Surface Mount
Compatible FPGAs Stratix, Stratix II, APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K, Cyclone, Cyclone II, Arria GX, Stratix GX, Stratix II GX —
Tindminan RoHS Non-compliant (legacy PQFP, lead-bearing) [DATA_NEEDED: RoHS compliance]
Programmable Type — In System Programmable (ISP via JTAG)
Supply Voltage (VCC) — 3.0 V to 3.6 V
Configuration Clock DCLK — [DATA_NEEDED: DCLK maximum frequency]
Active Supply Current (ICC active) — [DATA_NEEDED: ICC active typical value]
Standby Supply Current — [DATA_NEEDED: ICC standby typical value]
Storage Temperature — -65C to +150C
Package Code — QI100 (PQFP-100, industrial)
Level ng MSL — [DATA_NEEDED: MSL rating]
JTAG Standard — IEEE 1149.1 boundary-scan / ISP
Cascading — Supported (multi-device daisy chain)
Target FPGAs — Altera Cyclone, Cyclone II, Stratix series

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