EPF10K200SFC484-2X vs EPF10K200SFC484-2N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPF10K200SFC484-2X sa pamamagitan ng Intel at EPF10K200SFC484-2N sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPF10K200SFC484-2X | EPF10K200SFC484-2N |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Series | FLEX 10KS | — |
| Family | FLEX 10K | FLEX 10KE |
| Number of Logic Elements / Cells | 9984 | — |
| Number of LABs / CLBs | 1248 | — |
| Total RAM Bits | 98304 | — |
| Number of Gates | 200000 (typical) | — |
| Number of I/O | 369 | — |
| Core Voltage - Supply | 2.375 V to 2.625 V | — |
| Operating Frequency (max) | 250 MHz (family-typical, -2 speed grade) | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0°C to 70°C (Commercial) |
| Packhaging / Kaso | 484-BBGA (FineLine BGA) | — |
| Supplier Device Package | 484-FBGA (23 x 23 mm, 1.0 mm pitch) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Technology | CMOS, SRAM-based configuration | — |
| Configuration Memory | External serial (EPC1/EPC2 family compatible) | — |
| JTAG Support | IEEE 1149.1-1990 boundary-scan | — |
| Process Technology | [DATA_NEEDED: process node nm] | 0.22 µm CMOS |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | — |
| Logic Elements / Cells | — | 9,984 |
| Gate Count | — | 200,000 |
| Logic Array Blocks (LABs) | — | 1,248 |
| Embedded RAM Bits | — | 98,304 (96 Kbit) |
| User I/O Pins | — | 369 |
| Number of I/Os (alt spec) | — | 470 (per digchip datasheet summary) |
| Core Supply Voltage | — | 2.375 V to 2.625 V (2.5 V nominal) |
| Internal Performance | — | 200 MHz |
| Propagation Delay | — | 0.4 ns |
| Packhaging | — | 484-FBGA FineLine BGA, 23 x 23 mm, 1.0 mm pitch |
| Programming Interface | — | JTAG (IEEE 1149.1), SRAM configuration |
| I/O Standard Support | — | 5 V-tolerant, MultiVolt (1.8 V / 2.5 V / 3.3 V) |
| Logic Family | — | CMOS |
| Compliance / Lead Status | — | [DATA_NEEDED: RoHS status] |